Forced-Sleep SVR SRAM for High Frequency Applications

The present world with its fast-paced processing and data manipulation requires equally fast accessible data to match up to its performance and output. From temporary to permanent storage of data for the processors and devices, Static-Random-Access Memory (SRAM) has been one of the primary choices for industrialists, that it constitutes as memory in about 60% of the devices worldwide. Nevertheless, memories have proven to be one of the primary factors for power and delay issues in a handheld system, which demands the need for power optimization in memory devices at all times. This paper aims at designing and modifying the power dissipation in a single bit-cell of conventional 6T-SRAM to deduce a stable low power dissipating structure and verifies its stability by computing the performance parameter Power-Delay-Product (PDP) at various operating frequencies. The project made use of Tanner-EDA v16.01 to simulate the proposed structure and analyze the factors that contribute to power dissipation for optimizations. The proposed structure is observed to attain a power reduction of 62.273% compared to conventional 6T at an operating frequency of 2GHz. Furthermore, a 66.6033% decrease in PDP is also observed. Thus, a stable low power dissipating SRAM cell that is suitable for high frequency application is designed.