Carry Select Adder Based on Dual Rail Error Detection and Easy Testability

Concurrent error detection (CED) means detecting errors parallel with normal operation of the circuit. Proposed adder comprises of a carry select adder which can perform error detection and testability. Error can be detected by pure comparison. Comparing includes parity of the sum and predicted one and also carry outputs. Parity of the sum is generated by using XOR operation. Input patterns are produced for testing. Test patterns for different blocks have been designed. For future intelligent autonomous systems, this system is very important for finding accidents. Coding is done in Verilog HDL, simulated using ISIM Simulator and implemented using Xilinx ISE 14.7.