An investigation of clock-race conditions in NORA dynamic CMOS circuits

This paper investigates the clock-race condition of NORA pipelined logic circuits. It is shown that by specifying positive and negative clock skews, both n-p and p-n NORA pipelined logic circuits are sensitive to clock skews. These findings differ from those presented in the original paper [1]. To verify these observations, a NORA-based D-latch and two full adders are implemented using a 0.35 micron CMOS technology and are simulated using Spectre with the presence of both the positive and negative clock skews. The simulation results are presented.