A 1-to-4 SiGe BiCMOS Analog Demultiplexer Sampling Front-End for a 116 GBaud-Receiver

This paper presents a 116 GS/s analog demultiplexer front-end, sampling one differential input channel and routing it cyclically to 4 differential outputs at 29 GS/s each. With this topology, analog-to-digital converters can be time-interleaved to build a digitizing system with more than 100 GBaud, while keeping the necessary bandwidth under 15 GHz. Especially CMOS analog-to-digital converters benefit from this relaxed bandwidth requirement, which enables cost-efficient 116 GBaud silicon receivers for optical communications and instrumentation.