A PLL Frequency Synthesizer In 65 nm CMOS for 60 GHz Sliding-IF Transceiver

This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase /frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm
²
. The locking range of the proposed PLL is 23.328 ~ 25.92 GHz, the measured phase noise is -98.8 dBc/Hz@1 MHz, reference spur is -62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.