Phase Control Method for Subsampling PLL by Varying Phase and Frequency of Clock Signal of S/H Circuit

A phase control method for a subsampling phase locked loop (PLL) by varying the phase and frequency of the clock signal of a sample and hold (S/H) circuit is proposed. The proposed method uses a subsampling PLL that is advantageous for low phase noise. The phase of the output signal of the subsampling PLL is expressed as a product of the phase of the clock signal and the frequency ratio of the clock signal and the output signal. The proposed method enables phase control by varying the phase and frequency of the clock signal. Experimental results show that the phase control method yields the desired performance. The maximum phase difference obtained between the calculated and experimental results is 2.13° p-p.