Design and Implementation of an Efficient Buffer Management System for Network on Chip Routers

The paper presents an efficient first in first out (FIFO) buffer for use in network on chip routers for efficient management of data flow. Further we have designed a heterogeneous router using the efficient FIFO buffer, in which each channel can have a different buffer size. Even the FIFO of a particular channel is full it can borrow more buffer length from neighbouring channels. In this new architecture read and write operations are managed by the FIFO and channel itself, thus reducing the circuitry and making it a high speed router.