A 28–34-GHz Stacked-FET Power Amplifier in 28-nm FD-SOI With Adaptive Back-Gate Control for Improving Linearity

Adaptive back-gate control of a stacked-FET power amplifier (PA) in 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS is demonstrated for the 64-QAM signal at 28 and 31 GHz. Adaptive bias control (ABC) is applied to the back gate to effectively enhance the linearity of PAs for wideband waveforms with up to an 800-MHz envelope frequency. Third-order intermodulation distortion (IMD3), which degrades the linearity of a PA, is improved by adjusting back-gate biases of the stacked-FET PA according to the input power level without any concerns about wideband operation. From 28 to 34 GHz, the presented PA provides P
_1dB
and PAE
_P1dB
of 16.4-dBm and 37.3%, respectively. At 28 and 31 GHz, the measured P
_1dB
and PAE
_P1dB
are 17.4 and 16.9 dBm, 37.7% and 38.8%, respectively, with a compact core area of 0.088 mm
²
. The rms EVM improvement due to the linearity enhancement with the adaptive back-gate control is experimentally demonstrated to be around 2.6 and 1.8 dB for 8.65-dB PAPR single-carrier 64QAM signals with 8-dB back-off at 28 and 31 GHz, respectively.