0.5V 4.8 pJ/SOP 0.93\mu \mathrm{W}$ Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron

This paper proposes a scalable neuromorphic processor utilizing asynchronous routers and configurable LIF neuron models. The routing fabric's asynchronous protocol allows for critical timing paths between blocks to be relaxed and reduces power consumption of the global clock tree. The proposed neuron model allows users to deploy different leak profiles for different applications. Furthermore, a hardware mapper is also available to overcome the issue of fixed neuron core size when running networks with different number of neurons per layer. Our 16-core fabricated chip in 40 nm CMOS process works at a wide range of supply voltages. At 0.5V, its measured leakage is only
0.93\ \mu\mathrm{W}/\text{core}$
and its average energy efficiency is 4.8 pJ/SOP, which is 20% better than the state of the arts.