Scalability Analysis and Modeling of XPoint-based MRAM

The reduction of data movement between on-chip and off-chip memory is critical to achieve low power consumption on local devices, such as Internet-of-things. A potential solution is to develop more memory into a single chip. However, the conventional static-random access memory (SRAM) induces high power consumption with large area-overhead for the six-transistor memory cell. The emerging of the one-transistor one resistance (1T1R) nonvolatile memory overcomes SRAM with nearly-zero leakage power, high-density, and non-volatility. In addition, the cross-point (Xpoint) memory without transistor involved into the memory cell becomes promising solution to design ultra-high density memory. In this work, we present a Xpoint-based magnetic RAM (MRAM) using spin-orbit torque magnetic tunnel junction (SOT-MTJ). We provide a balance write scheme to SOT-MTJ and an odd-even array structure to mitigate the sneak current. Moreover, we analyze the impact factors on scalability and stability. The simulation model is developed to evaluate the performance of the proposed Xpoint-based MRAM.