Low-Voltage High-Linearity Differential Input Buffer with CurrentAmplifier Feed-Forward Compensation for High-Speed ADCs

A source-follower (SF) based differential input buffer for high speed ADCs, in which an auxiliary SF pair and a current amplifier pairs generate a differential compensation current injecting into the main SF pair to achieve linearization is presented. Designed in a 28nm CMOS, the two tone simulation (1.4-Vpp input at 5.92GHz and 5.98GHz) result with 6-GSPS sampling frequency, and 2.5-V VDD supply voltage shows that the buffer achieves an SFDR of 76.3dBFS, equivalent input noise about 200uV and offet 1mV at most while consumes only 150-mW power(Differential pair). Compared to the conventional structure, the proposed input buffer is more suitable for low-power and low-voltage applications, and brings smaller capacitive load to the input source.