Phase Synchronization Technique Between Fractional-N PLLs by Correcting Phase Error due to Cycle Slip using Reference Delta-Sigma Modulator

This paper proposes a phase synchronization technique between multiple fractional-N PLLs. By matching an operating state of a DSM, which is driven by a multi-modulus divider (MMD) output, and that of a Reference DSM, which is driven by a reference clock, phase error between PLLs can be removed. The proposed PLL was fabricated in a 0.13um SiGe BiCMOS process, and successfully removed a phase variation between two PLLs.