Digitally Assisted Secondary Switch-and-Compare Technique for a SAR ADC

This brief presents a secondary switch-and-compare technique to improve the energy efficiency of a SAR ADC with minimal area and power overheads. The method exploits the self-calibrated comparator in the SAR ADC to generate a supplementary LSB. Instead of a C-DAC, this switching scheme produces voltage change required to evaluate the supplementary LSB at the calibration node of the comparator. The (N+1)
^th
bit logic proficiently controls the secondary switching and assists the comparator in resolving the augmented LSB. A proof-of-concept (9+1)-bit 20 kS/s SAR ADC is designed in a standard 180 nm CMOS technology to demonstrate the proposed technique. The post-layout simulation results achieve energy efficiency of 51.2 fJ/conv.-step at 562 nW of average power consumption from V
_DD
of 1.8 V.