Approximate TMR Based on Successive Approximation to Protect Against Multiple Bit Upset in Microprocessors

This work proposes the use of Triple Modular Redundancy (TMR) to mitigate multiple bit upsets affecting embedded software. To reduce the TMR's overhead, we propose to exploit approximate computing paradigm and, more in particular, the so-called successive approximations technique. The proposed approach, called Approximate TMR (ATMR), leverages the nature of successive approximation technique to improve fault masking. Successive approximation algorithms are based on loop computations that approximate to a final result on each iteration. By varying the number of iterations, one can observe differences in the fault masking and execution time. Therefore, a trade-off has to be identified between the number of iterations (i.e., the degree of the approximation) in the ATMR and its capability on correcting errors. A set of algorithms were implemented as embedded software in the ARM Cortex A9 processor of Xilinx Zynq-7000 series board. Experiments consist of exposing the finned processor to laser pulses at the data cache memory area provoking bit-flips. Results show that the ATMR approach decreases the execution time overhead compared to the classical TMR while keeping an acceptable fault masking rate.