Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients

New design methodologies are needed to improve the circuit robustness to deal with technology scaling issues. Traditional fault-tolerant approaches present severe overheads. Alternative solutions based on partial fault tolerance and fault avoidance are considered a possible solution to the reliability problem. An accurate evaluation of circuit reliability is fundamental to allow a reliability-aware automated design flow, where the synthesis tool could rapidly cycle through several circuit configurations to assess the best option. Most of the circuit reliability estimation methods use logic gate information as the starting point. The difference in logic gates reliability is neglected. This work proposes models capable of analyzing logic gates susceptibility in different abstraction levels. Three methods are proposed based on transistor arrangement, stick diagram, and layout of the logic gates. A 45nm standard cell library is used to validate the proposed methods. The achieved results are used to analyze ISCAS'85 benchmark circuit reliability. The obtained Mean Time Between Failures (MTBF) shows a considerable reduction of almost 50% compared to the values from traditional fixed logic gate reliability.