A 12-to-15 b, 100-to-25 kS/s Resolution Reconfigurable, Power Scalable Incremental ADC Using Ultrathin Chips

Resolution reconfigurable Nyquist-rate analog-to-digital converters (ADCs) are able to deliver an optimized end-to-end power efficiency when a single ADC is time-multiplexed between different sensors. In this letter, a 12-to-15b resolution reconfigurable power scalable Nyquist-rate incremental ΔΣ (I-ΔΣ) ADC, operating at sampling rates from 100 to 25 kS/s, is proposed. A widely reconfigurable dynamic range (DR) (73-92 dB) with fine selection granularity is achieved by incorporating a scalable first integrator and optimally setting the oversampling ratio (OSR) of the ΔΣ modulator. A 2.5× power reduction is measured for the proposed technique in comparison to a pure OSR-based resolution scaling. A Walden figure-of-merit (FoM
_W
) of 880 fJ/conv.-step and Schreier (FoM
_S
) of 160.3 dB are measured in the 14b mode. The I-ΔΣ ADC is fabricated in a 180-nm CMOS technology and consumes 0.48 and 0.93 mW from a supply voltage of 3 V at the 12b and 15b modes, respectively. By exploiting the back-thinning of the ADC chips, the presented 30-μm-thick ADC becomes readily available for integration into hybrid flexible sensor systems.