Laser Processing For 3D Junctionless Transistor Fabrication

To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475°C process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 10
¹⁹
at/cm
³
) poly-silicon film featuring excellent roughness values (R
_max
= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.