A machine independent WCET predictor for microcontrollers and DSPs [worst case execution time]

This paper describes a method for analyzing and predicting the timing properties of a program fragment. The paper first presents a language implemented to describe a processor's architecture and a static worst case execution time (WCET) estimation method is then presented. The timing analysis starts by compiling a processor's architecture program followed by the disassembling of the program fragment. The assembler program is then decomposed into basic blocks and a call graph is generated. These data are later used to evaluate the pipeline hazards and cache miss that penalize the real-time performance. Finally, some experimental results of using the developed tool to predict the WCET of code segments with some Intel microcontrollers are presented.