SRAM Utilization and Power Consumption Analysis for Low Power Applications

In digital systems memories are very essential elements. Memories usually consume higher percentage of power in the entire designed system. As portable and handheld devices that operate on batteries, limited consumption of power is required by the design modules. Since decades the researchers design criteria targeted to lower the power utilization and to improves the device performance with less power consumption. This paper projects the research carried out to design a Static Random Access Memory (SRAM) cell with minimum power that result to lower leakage currents and power consumption suitable for low power applications.