Impact of Process Variations on the Capacitance and Electrical Resistance down to $1.44\ \mu\mathrm{m}$ Hybrid Bonding Interconnects

With the rising of Hybrid Bonding (HB) as an interesting solution for fine-pitch 3D integration, the influence of process induced variations on performances is a demanding and crucial task. A 3D stacked test vehicle with hybrid bonding pitch ranging from 6.8 down to 1.44 μm was processed and analyzed. A deep analysis on the influence of process variations is conducted and correlated to electrical measurements thanks to a dedicated simulation methodology. This allows a better understating of the process variation parameters that affects electrical resistance and capacitance along with their relative importance which is essential for optimization. The common parameter affecting both capacitance and electrical resistance is Wafer-to-Wafer overlay between top and bottom wafers arising the need for high accuracy in bonding alignment. The quality of the hybrid bonding interface is discussed thanks to the simulation model, before and after robustness tests depending on hybrid bonding pitch, leading to an estimation of contact resistivity around 2. 10
^-10
Ω.cm
²
for the 1.44 μm-pitch structure.