A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor

A proactive clock-gating system (PCGS) in a 7-nm Qualcomm
^®
Hexagon™ digital signal processor (DSP) improves performance or energy efficiency by reducing the magnitude of supply voltage ( V
_DD
) droops. The PCGS integrates a digital power meter (DPM) to monitor the power per cycle based on microarchitectural events and a voltage-clock-gating (VCG) circuit with a power-delivery-network (PDN) model to predict the V
_DD
response to DPM power changes. When the PDN model anticipates a potential V
_DD
-droop violation, the VCG adapts the clock frequency ( F
_CLK
) by gating the global clock to reduce the actual V
_DD
-droop magnitude. Silicon measurements of the PCGS in the 7-nm DSP demonstrate a 10% higher F
_CLK
or 5% lower V
_DD
.