Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods

When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable information is often lost during physical synthesis. This article proposes HiDaP, a novel multilevel algorithm that uses RTL information and analytical methods for the macro placement problem of modern designs dominated by multicycle connection pipelines. By taking advantage of the hierarchy tree, the netlist is divided into blocks containing macros and standard cells, and their dataflow affinity is inferred considering the register latency and flow width of their interaction. The layout is represented using slicing structures and generated with a top-down algorithm capable of handling blocks with both hard and soft components. An adaptive multiobjective cost function is used to simultaneously minimize wirelength, timing, overlap, and distance to preferred locations, which can be user defined or generated by analytic methods (spectral and force directed). These techniques have been applied to a set of large industrial circuits and compared against state-of-the-art commercial and academic placers, and also to handcrafted floorplans generated by expert backend engineers. The proposed approach outperforms previous algorithmic methods and can produce solutions with better wirelength and timing than the best handcrafted floorplans. Post-routing layouts are almost brought to timing closure and DRC cleanness with minimal engineer modification, showing that the generated floorplans provide an excellent starting point for the physical design flow and contribute to reduce turn-around time significantly.