A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection

We propose a power-aware toggling-frequency actuator for an 1K-byte data-toggling SRAM. The actuator periodically toggles the stored data to balance the voltage stress in the SRAM cells to secure against data imprinting attacks. Our proposed actuator has three key features. First, our proposed actuator embodies a small duty cycle clock divider to divide the main clock and generate two toggling clocks. The small duty cycle clock minimizes toggling transistor turn-on time and reduces the leakage power in stand-by operation. Second, it leverages on the main clock of the data-toggling SRAM to generate the toggling clock without an additional clock generator. Third, our proposed actuator can scale the data toggling operation between high frequency for highly secure applications, and low frequency for low power applications. We implemented the 1K-byte data-toggling SRAM with the proposed toggling-frequency actuator based on 65nm CMOS technology. At higher toggling frequency (~ 1MHz), the data-toggling SRAM features less than 5% imprinting effect. At lower toggling frequency (~ 10kHz), the SRAM dissipates <; 0.1mW toggling power where the secure data protection is less critical. When compared against the reported counterpart with toggling clock of 50% duty cycle, our proposed data-toggling SRAM (with ~ 3% duty cycle clock divider) occupies ~ 31% smaller IC area and dissipates ~ 29% lower toggling power, resulting in an overall reduction of ~ 51% area ×power product.