Noise Margin Calculation in Multiple-Valued Logic

Noise margin (NM) is an important concept in circuit design since noise is one of the major challenges for reliability. This subject is very critical in multiple-valued logic (MVL), where the entire voltage range is divided into several narrow zones. Ternary NMs are currently calculated based on a conventional definition. In this paper, we use another slightly different definition to present a new set of equations. Our investigations show that the proposed equations are more accurate and return closer results to reality. Furthermore, the given explanations are extended beyond ternary logic in this paper for MVL NM calculations in higher radixes.