An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group

Nowadays, the verifiable delay function (VDF) is widely regarded as the core function for the next-generation blockchain system because it is slow to evaluate but easy to verify. In general, the squaring operation takes a significant proportion of VDF computation. Moreover, the squaring over a class group, including large-number extended greatest common divisor (GCD) computations, divisions, and multiplications, is extremely hard to be accelerated in hardware. In this paper, for the first time, we propose an efficient architecture for squaring by utilizing many algorithmic transformations and architectural optimizations to reduce the critical path and calculation cycles. Firstly, the squaring algorithm is modified to achieve partial parallel computing, and a very hardware-efficient extended GCD algorithm is selected to reduce the whole computation cycles. Secondly, highly-parallelized architectures for large-number division and multiplication are devised respectively. Finally, the proposed architecture is coded using hardware description language (HDL) and synthesized under the TSMC 28-nm CMOS technology. The synthesis results show that the proposed design with the input width of 2048 bits averagely takes 6.319us per squaring at a frequency of 500 MHz. Compared to the original squaring with the same setting running over an Intel(R) Core(TM) i7-6850K 3.60GHz CPU, our design achieves about 2x speedup.