Testing of Configurable 8T SRAMs for In-Memory Computing

In-memory computing (IMC) architecture has been considered as an alternative for overcoming the memory wall of von-Neumann computing architecture. Various IMC memories using 8T static random access memory (SRAM) cell have been reported. Some of them, the memory array can provide SRAM and ternary content addressable memory (TCAM) function. In this paper, a March-like test algorithm is proposed, which requires 10 × 2
^p
Read/Write operations, (2
^q
+ 4m) Compare operation, and (2
^r+1
+ 4m) Erase operations to cover simple SRAM faults and TCAM Comparison faults, for an IMC 8T SRAM providing 2
^p
×w-bit SRAM and m× 2
^q−1
-bit TCAM, where p = q+r and m = 2
^r
×w.