Optimize Multiple-Output Logic Designs using Randomization

While single-output combinatorial logic implementation has been studied for many years, the focus of this paper is to jointly optimize several combinatorial outputs. At the end of the optimization process, the user is presented with a range of designs having various areas and propagation delays. Our technique uses randomization, and this has the advantage of being able to create unconventional designs, devoid of any human bias. The purpose of this research is to increase the cost-effectiveness of building components of a chip, while simultaneously increasing its clock speed.