An FPGA-based Optimized Memory Controller for Accessing Multiple Memories

Memory bandwidth is an essential constraint while implementing computationally intensive applications on the Field Programmable Gate Array (FPGA). To achieve high performance, the computational core must be able to process data at the highest possible data rates. The memory bandwidth can be significantly increased if multiple data words are accessed from multiple memory banks simultaneously. The increase in memory bandwidth will positively impact the overall performance of the FPGA-based accelerators.In this paper, we present an optimized memory controller that enhances memory bandwidth. Our optimized memory controller is capable of reading and writing data to multiple memories. Additionally, the memory controller performs pipelined read, execute, and write operations which helps to increase the performance of the computational core implemented on an FPGA. We also present the Natural Logarithm hardware implementation used to show the merits of the memory controller being optimized. Our experiments demonstrate that the results obtained using our optimized multi-memory controller is 30X and 7X faster than software and OpenMP implementation executing the Natural Logarithm function on the conventional multi-core processor.