Implementation of a Hermitian decoder IC in 0.35 /spl mu/m CMOS

This paper presents the first integrated circuit implementation of a Hermitian decoder thereby proving its practical viability. Hermitian codes provide much larger block lengths (n = 4080) compared to that of the popular Reed-Solomon (RS) codes (n = 256) over the same field (GF(256)). This translates to a coding gain of 0.6 dB for the same rate. However, Hermitian codes were deemed to be too complex to implement until the emergence of a recent algorithmic breakthrough which made the complexity of Hermitian decoders comparable to that of RS codes. Based on Koetter's decoding algorithm, the chip architecture consists of an array of sixteen interdependent Berlekamp-Massey algorithm (BMA) blocks. Thus, the same IC can be used for decoding RS codes as well. The decoder IC is designed in a 3.3V, 0.35μm, four-metal CMOS process and can correct up to t = 60 errors per block of n = 4080 words at a rate of 400 Mb/s. The IC prototype consumes 3.0 W with a 50 MHz clock.