Optimization of Physical Layer Modules of USB 3.0 Using FPGA

Super speed bus communication is achieved through USB 3.0 architecture due to its dual-bus architecture. The main purpose of this research work is to reduce the power consumption and area occupancy due to the different components of the physical layer of the USB 3.0. This research work has implemented the scrambler, 8b/10b encoder modules through a low power consumption approach. The implementation of scrambler and 8b/10b encoding modules are performed on two different FPGA i.e. Kintex-7 KC705 Evaluation Platform (xc7k325tffg900-2) and ZedBoard Zynq evaluation and development kit (xc7z020clg484-1) both are based on 28nm technology. The result of power utilization, area consumption of chip and different parameters are compared. The power obtained and area utilized by Kintex-7 of scrambler circuit is 0.26% and 6.34% lesser compared to ZedBoard and similarly for 8b/10b encoder power and area utilization is reduced by1.5% and 6.96%. The proposed research work has designed the scrambler and 8b/10b encoder modules of the USB 3.0 using Xilinx ISE tool and implements the verilog codes on it by generating the FPGA report.