Design of Schmitt Trigger Using DTMOS Technology for Low power Consumption

This research work presents a design of Schmitt trigger using dynamic threshold voltage metal oxide silicon (DTMOS) for low power consumption. The proposed DTMOS Schmitt trigger design and simulated in 180nm technology in CADENCE tool and operated in 0.3V supplied power. The main idea behind this project is to reduce power consumption and noise figure. It is used to remove noise from signals used in digital circuits instead use of CMOS can result in increasing the power and noise. Experimental analysis demonstrated the performance of DTMOS Schmitt trigger for low power and less area which further helps to improve the functionality of the circuit.