Review of Neuro-Space Mapping Modeling for Packaged Transistors

This article reviews the Neuro-space mapping (Neuro-SM) modeling method for packaged transistors. In this method, neural networks are used to model the DC, the small-signal, and the large-signal characteristics of packaged transistors. An improved mapping circuit structure is introduced. A method is used to separate the DC and AC components of the current and voltage signals. Modeling examples on laterally diffused metal-oxide semiconductor (LDMOS) transistor AFT18S230 can show that the Neuro-SM modeling method can accurately match device data, and improve modeling efficiency.