VHDL implmentation of a BCH minimum weight decoder for double error

Normally the decoder of a communication system is more complex than the encoder. Many different decoding algorithms have been introduced for cyclic linear block codes. Minimum Weight Decoding (MWD) is a simple decoding technique for cyclic linear block codes with low complexity. This paper describes in detail the VHDL (VHISC Hardware Description language) design implementation of a Hard-Decision Minimum Weight Decoder. The decoder has been implemented for BCH (15, 7, 5) code which is capable of detecting and correcting double errors. The simulation result for each part of the decoder is presented in this paper which shows how the decoder can detect and correct any double error pattern. The algorithm was first implemented by writing a C-program to verify the correctness of the algorithm and then the decoder was implemented in VHDL. An FPGA (Field Programmable Gate Array) is the target technology of this decoder.