Modified Interface Algorithm of PHIL Simulator to Improve Harmonic Current Accuracy

In Conventional FCF (Feedback Current Filtering) interface algorithm of PHIL (Power Hardware-in-the-Loop) simulator, LPF (Low Pass Filter) is used to reduce the input harmonic currents of the PHIL simulator. The reduced harmonic currents help the PHIL simulator to operate in a wider variety of interface filter conditions. However, the simulation results of FCF using the LPF are not constant and vary with the interface filter, DUT (Device Under Test) and PHIL simulator switching frequency. To make the simulation results constant, this paper proposes a digital filter to replace the LPF and a modified interface algorithm. The proposed digital filter based on integral average can remove the harmonic currents of specific frequency. The output harmonic voltages of PHIL simulator due to the input harmonic currents are not generated. Hence, the simulation results are constant regardless of the DUT and PHIL simulator switching frequency. The proposed interface algorithm injects the harmonic voltage of DUT output in PHIL simulator output voltage. Because the harmonic current outputs of DUT are able to be controlled by the amplitude of the injected harmonic voltages, the proposed interface algorithm can obtain the constant simulation results regardless of the interface conditions. Several experimental results are presented to verify the usefulness of the proposed digital filter and interface algorithm. Also, the switching frequency conditions of DUT and PHIL simulator for the proposed interface algorithm to operate effectively are check experimentally.