Revisiting Inherent Noise Floors for Interconnect Prediction

Today's synthesis, placement and routing (SP&R) tools routinely handle millions of instances. Accurate prediction of outcomes is needed to avoid long wasted runtimes from, e.g., unroutable floor-plans or placements. However, tool outputs have inherent noise that implies a lower bound on prediction error [10] [7]. The goal of interconnect prediction naturally raises a question of “How accurate can interconnect prediction be?" In this work, we revisit the topic of inherent noise and “chaos" in IC implementation flows, to characterize current noise floors on interconnect prediction. We study effects on commercial P&R tool outcomes of such previously-identified noise sources as reordering and renaming in instance cells, nets, and master cells. We also perform studies for macro placement, by slightly shifting the location of macro placement blockages in the center of the layout floorplan. We find that recent commercial tool versions still show significant routed wirelength noise of up to 7% when netlist reordering is applied, and 11.5% when macro placement blockages are shifted. Finally, we also raise the question of “How should predictions be used?” by showing example scenarios where advance knowledge of physical design outcomes can potentially worsen noise and predictability.