Reducing Systematic Defects using Calibre Wafer Defect Engineering and Machine Learning Solutions

As the semiconductor manufacturing continues its march towards more advanced technology nodes, design and process introduced systematic defects become significant yield limiters [1]. Therefore, identification and characterization of these systematic defects becomes increasingly important. The design systematic defect analysis is normally done by combining both inline inspection results and physical layout (design) information. In the full flow, from preparing inspection care area to performing systematic defect root cause analysis, utilizing EDA software plays an important role. Especially with machine learning technique combining with OPC feature vector extraction, we can have a more precise analysis of the weak pattern on wafers. In this paper, we will introduce how we utilize these techniques for Process Window Qualification (PWQ), focus mainly on how we perform BFI to SEM down sampling, and full chip hotspot prediction to verify potential hotspots on PWQ wafer in order to obtain an accurate process window, and identify systematic weak patterns with increased SEM defect hit rate.