Energy-Efficient and Error-Resilient Cognitive I/O for 3-D-Integrated Manycore Microprocessors

Editor’s note:
This article presents a novel framework that combines a QoS-aware memory partitioning scheme and a reinforcement-learning-based I/O voltage-swing tuning for energy-efficient and reliable processor-DRAM subsystem design. —
Sudeep Pasricha, Colorado State University