Mis-match characterization of 1.8 V and 3.3 V devices in 0.18 /spl mu/m mixed signal CMOS technology

This paper studies the mis-match characteristics of 1.8 V and 3.3 V multiple threshold voltage devices, including nominal V/sub t/, medium V/sub t/ and native devices in 0.18 /spl mu/m mixed signal CMOS technology for precision analog design. Three test structures, cross couple, stripe pair and parallel patterns, are presented to investigate the structure dependent mismatch behaviour. Matching characteristics of four analog parameters: V/sub t/, I/sub dsat/, /spl beta/ and G/sub ds/, are investigated in terms of device size, layout configuration and process condition. An additional analytical model of current mis-match including V/sub t/, /spl beta/, source and drain series resistance and carrier velocity factor has been verified, in addition to global distortion of gate oxide thickness and substrate doping concentration.