C-V extraction method for gate fringe capacitance and gate to source-drain overlap length of LDD MOSFET

Gate to source-drain overlap length becomes a more critical quantity in device modeling as the channel length of the transistor decreases. In this paper, we present an improved capacitance-voltage measurement method for determination of the gate to source/drain overlap length and the gate to source/drain overlap capacitance, which is applicable to deep sub-micrometer devices. To obtain exact results, we have taken into account the effects of various parasitic components which mainly come from measurement equipment, test structures, and the device itself, such as the gate sidewall fringe capacitance.