Verification of Non-linear Arithmetic Circuits using Functionally Reduced And-Inverter-Graph (FRAIG)

This paper presents a methodology for verifying non-linear arithmetic circuits by applying diffident concepts. In our proposed methodology, a combination of gate-level netlist, Functionally Reduced And-inverter Graph (FRAIG) and Taylor Expansion Diagram (TED) is used to verify that the implementation satisfies the specification. Backward algebraic rewriting technique is used for function extraction of the word-level abstraction. Gate-level netlist is adopted to form FRAIG graph which is verified via TED representation. This is intended to handle the complex verification process of multiplier and alternatives of the traditional AIG for arithmetic circuits. Experiments are conducted on both post and pre synthesized non-linear arithmetic circuit of various multipliers such as Booth and CSA. The results win by several order of magnitude in area consumption, were the used area is almost 50% less than other compared approaches with a slight increase in CPU run time.