A New Structure of ILD Gap Filling Improvement for Floating-Gate Memory

For traditional stack gate type nonvolatile memory, high voltage apply to the control gate and well during PGM and ERS operation, this requires high break down voltage(BV) for I/O Tr. One usual method to archive high BV I/O Tr is increasing LDD energy which requests thick enough poly thickness for peripheral gate to avoid implant penetration. As the scaling of the dimension, for conventional floating gate structure poly space aspect ratio at flash array area becomes much high, in case of this, potential risk of reliability and yield loss will be induced if ILD gap fill capability is not enough among adjacent control gate. To solve this issue, in this paper, a novel dual poly structure and process flow is proposed, this dual poly structure can decrease control gate poly thickness of flash array area, while the poly thickness in the logic area keeps no change. The proposed dual poly structure decreases the memory aspect ratio effectively and independently to peripheral and improves the ILD gap filling window. Good yield and reliability results are obtained by process optimization of dual poly structure, and this novel new structure is an important candidate for further scaling of stack gate type flash.