Design and Development of 3D WLCSP for CMOS Image Sensor Using Vertical via Technology

Wafer-level chip scale packaging (WLCSP) using tapered through silicon via (TSV) has been widely applied in CMOS image sensor (CIS) in mass production. The mass production technology now is using laser drill and surface landing, which has been shown in Fig. 1. However, as the increase of IO numbers and reduction in chip size, there is no enough space for ball placement when using these two structures. Meanwhile, side wall delamination and function layer crack are often found in strict reliability conditions. To satisfy small chip size packaging requirement and pass higher reliability test, we propose a new design of WLCSP with vertical TSV which can effectively reduce the stress of pad in temperature cycle (TC) test. The finite element simulation evaluation and key processes including via etch, redistribution layer (RDL) lithography and solder mask formation are also presented.