Signoff-level full-chip ESD/reliability design verification using logic-driven layout static approach

An automated signoff-level full-chip design verification methodology for electrostatic discharge (ESD) protection is established in foundries, integrated device manufacturers (IDMs), and semiconductor design houses. This methodology employs a static rule check approach implemented by electronic design automation (EDA) tools using logic-driven layout (LDL) check functionality [1]. It can not only examine ESD protection circuits on logical circuitry, but also correlate check criteria to corresponding layout geometrical data and electrical resistor networks. This methodology aligns well with foundry/IDM/design house ESD design guidelines, enabling ESD design kits to provide practical ESD signoff verification for tapeout. In this paper, we describe topological IO-ESD, cross-power-domain ESD, and physical ESD path robustness design verification using the LDL check methodology.