The Solution of AIO-ET Via Open and Process Window Improvement

With the development of VLSI (Very Large Scale Integrated Circuits) manufacture, the continuous shrinkage of line width critical dimensions should meet high performance and high integrated level of device requirement. More and more new materials and new processes were introduced to meet the process requirement of critical layer. This paper investigates the solutions of the via open and the window improvement of All in One etch (AIO-ET). In this paper, Transmission Electron Microscope (TEM), Wafer Acceptance Test (WAT) and Chip Probing (CP) were performed to evaluate the etch process.