Decreasing the Power Dissipation and Switching Time in Hybrid AND Gate Logic Circuit

Any electronic circuit design's major goal is to get characteristics near to ideal characteristics such as less power dissipation, reduces the switching time, and how to control switching time. Due to lots of benefits of logic gates, such as faster to solve many complex problems, there are building blocks of any digital device, so in a nutshell, digital devices want not to work without them. In this paper, two models of the AND logic gate will be designed and simulated. The first model is the traditional 2-input AND logic gate "utilizing just CMOS" and the second is hybrid CMOS-NEMS to achieve a new 2-input AND logic gate model. These two models will be designed by utilizing MATLAB/Simulink. The power dissipation and switching time for two models were analyzed. A comparison between the hybrid model and the traditional model of AND logic gate will be carried out. The initial results displayed significant enhance in the characteristics of hybrid mode where the falling time at hybrid case is 396ns, but at traditional case is 712.8ns. This means that the present decrease in hybrid is 44.4% less than the traditional case and a small reduction in rising time from79.2ns to 79ns, so the switching time at hybrid case is less than the traditional case. In addition, the power dissipation at hybrid case is 15μW, while at the traditional case is 25μW, so that the present decrease in power dissipation is 40%.