A study of underlayer geometry effects on interconnect line characteristics through S-parameter measurements

IC interconnect transmission line effects due to the characteristics of a silicon substrate and crossing metal lines and current return path impedances are physically devised and experimentally characterized. Test transmission line patterns having several underlayer geometries are devised and measured for line parameter characteristics by S-parameter and for signal responses by time domain reflectometry. They are designed and fabricated with a 0.13 /spl mu/m CMOS DRAM technology. Through this work the effects of underlayer line structures on line parameter differences and signal distortions are studied. The results are useful in gaining a deep understanding of the skew balance of package leads or global signal lines such as clock line and high-performance data lines.