A 0.9V All Digital Synthesizable OPAMP with Boosted Gain and Widened Common Mode Input Range

This paper presents a fully digital synthesizable Operational Amplifier (OPAMP) based on digital standard cells. The OPAMP's gain is enhanced by the combination of the all-inverter-based negative resistance loads and the four-stage cascade structure with Nested Feed Forward Compensation (NFFC). Moreover, this paper uses NAND-NOR pairs to improve the common mode input range. Since the proposed OPAMP only consists of digital standard cells, it is described in Verilog code, and its layout is implemented using automatic placement and route (APR) tool. The proposed circuit is implemented in 28nm CMOS and the post-layout simulation results show that the proposed circuit achieves a DC gain of 35dB and a unity gain bandwidth (UGB) of 1.73GHz under 0.9V power supply.