Power-Aware Timing Analysis for High-Speed Memory Interface

As the speed of advanced memory products exceeding multi-GHz range, signal integrity (SI) and power integrity (PI) analysis becomes imperative to ensure robust timing performance. This paper will explore a couple of methodologies of on-chip power delivery network (PDN) modeling, and provide a flexible and accurate simulation flow for power-aware timing analysis. Power supply induced jitter (PSIJ) will be examined for 8Gbits LPDDR5 mobile products with a data rate up to 6400Mbps using 1y-nm DRAM process. Package and SoC (system-on-chip) co-simulation can be included as well to extend the PI analysis into system level.