Design and Implementation of 64-bit Parallel Prefix Adder

Binary addition is a commonly used application in computational arithmetic. Adders are the basic building blocks of the various computational structures leading to wide applications in Digital Signal Processing, arithmetic, and logical units, microprocessors, and microcontrollers. Research on adders with optimal specifications is continuously carried out. The delay of an adder depends on the speed of the carry bit to reach the next bit position for addition. In this paper, we introduce and discuss a fast 64-bit parallel prefix adder design. The proposed novel design uses the advantage of the Ling adder design needed to suppress the area requirement and increase the computation speed compared to the existing algorithms. With a moderate increase in area and power, the adder gives a quality critical path delay of 21.9ns. The structure is coded using Verilog HDL, simulated, and implemented with the Xilinx Vivado tool.