An Efficient Multiplier-less Hardware for Hidden Periodicity Detection Using Ramanujan Filter Bank

This paper presents an efficient multiplier-less architecture of hidden periodicity detector (HPD) using Ramanujan Filter Bank and its implementation on FPGA. The proposed hardware finds usage in many practical applications e.g. finding hidden periodicities in DNA and proteins, detecting absence seizures in the EEG signal, identifying periodic movements of cosmic bodies, etc. The algorithm used for hidden periodicity detection is based on Ramanujan Filter Bank (RFB). The novelty of the present work is in making the first attempt in designing dedicated hardware for hidden periodicity detection. Two different architectures based on RFB have been proposed - a classic architecture and a multiplier-less architecture. These are structurally modeled in Verilog HDL and implemented on Artix 7 FPGA kit. The multiplier-less architecture utilizes fewer hardware resources and is faster than the classic one due to a lower critical path delay. Thus, lesser chip area and higher operating frequency are achieved. The dedicated hardware is shown to be more than 1000 times faster than its software counterpart. An ideal hidden periodicity detector has also been introduced to present an accuracy analysis of the proposed architecture but the analysis is applicable for all kinds of hidden periodicity detectors.